Regviz

NXP Semiconductors /NeoM3 /FLASHCTRL /ENCLR

Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text Text

Interpret as ENCLR

Share

Cut and paste this URL to share the unmodified register and value:

https://regviz.com/r/NXP Semiconductors/NeoM3/FLASHCTRL/ENCLR#0x0

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0RESERVED0 (RDWR_CLR_EN)RDWR_CLR_EN 0RESERVED 0 (PROG1_CLR_EN)PROG1_CLR_EN 0RESERVED

Description

EEPROM interrupt enable clear

Fields

RESERVED

Reserved. Read value is undefined, only zero should be written.
RDWR_CLR_EN

Clear read/write operation finished interrupt enable bit (EEPROM). 0: leave corresponding bit unchanged. 1: clear corresponding bit.
RESERVED

Reserved. Read value is undefined, only zero should be written.
PROG1_CLR_EN

Clear program operation finished interrupt enable bit for EEPROM device 1. 0: leave corresponding bit unchanged. 1: clear corresponding bit.
RESERVED

Reserved. Read value is undefined, only zero should be written.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data